Image processing engine exploits soft hardware

Designed from the ground up to enable OEM customers to implement ultra high speed algorithms in a scaleable embedded environment, leaving the host PC free for other tasks

Showing in Europe for the first time at IPOT 2005 is Coreco Imaging's new flagship image processing engine, the Anaconda.

It has been designed from the ground up to enable OEM customers to implement ultra high speed algorithms in a scaleable embedded environment, leaving the host PC free for other tasks.

Building on Coreco's Trigger to Image Reliability framework, which was launched with the X64 series, the Anaconda's design features a robust acquisition control unit (ACU) and a data transfer engine (DTE) that can accommodate multiple simultaneous transfers enabling original, intermediate and result image data to be delivered to the host.

The Anaconda's image processing unit (IPU) contains two independent image processors which can be run in parallel or in a pipeline configuration.

The first is a large field programmable array logic processor (FPGA) or, put more simply, 'soft hardware'.

Developers are free to implement their own hardware algorithms or link together Coreco Imaging developed standard designs.

Programming can be done using standard VHDL development toolsets or Celectica's DK3 that enables C-like programming of the hardware.

The second image processor is a Power PC module that is supported by Metrowerks Code Warrior.

Developers are free to write their own code or link together any of Coreco Imaging's library functions such as the robust Smart Search.

2Gb of image memory is available to the programmer with a sustainable data bandwidth of 5.3Gb/sec, removing any design bottleneck issues.

The Anaconda is currently available in CameraLink or LVDS formats and is compatible with PCI 32 (3.3v), PCI 64 and PCI-X.

Applications include film scanning, AOI, high speed web inspection, among others.

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